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rev. 0.02 / apr. 2009 1 204pin ddr3 sdram sodimm ** contents are subject to ch ange without prior notice. ddr3 sdram unbuffered 4gb sodimm based on 2gb a version hmt351s6afr8c
rev. 0.02 / apr. 2009 2 hmt351s6afr8c revision history revision no. history draft date remark 0.01 initial release feb. 2009 preliminary 0.02 added idd specification apr. 2009
rev. 0.02 / apr. 2009 3 hmt351s6afr8c table of contents 1. description 1.1 device features and ordering information 1.1.1 features 1.1.2 ordering information 1.2 speed grade & key parameters 1.3 address table 2. pin architecture 2.1 pin definition 2.2 input/output functional description 2.3 pin assignment 3. functional block diagram 3.1 4gb, 512mx64 module(2rank of x8) 4. absolute maximum ratings 4.1 absolute maximum dc ratings 4.2 operating temperature range 5. ac & dc operating conditions 5.1 recommended dc operating conditions 5.2 dc & ac logic input levels 5.2.1 for single-ended signals 5.2.2 for differential signals 5.2.3 differential input cross point 5.3 slew rate definition 5.3.1 for ended input signals 5.3.2 for differential input signals 5.4 dc & ac output buffer levels 5.4.1 single ended dc & ac output levels 5.4.2 differential dc & ac output levels 5.4.3 single ended output slew rate 5.4.4 differential ended output slew rate 5.5 overshoot/undershoot specification 5.5.1 address and control overshoo t and undershoot specifications 5.5.2 clock, data, strobe and mask ov ershoot and undershoot specifications 5.6 input/output capacitance & ac parametrics 5.7 idd specifications & measurement condtiions 6. electrical characteristics and ac timing 6.1 refresh parameters by device density 6.2 ddr3 standard speed bins and ac para 7. dimm outline diagram 7.1 4gb, 512mx64 module(2rank of x8)
rev. 0.02 / apr. 2009 4 hmt351s6afr8c ? vdd=vddq=1.5v ? vddspd=3.0v to 3.6v ? fully differential clock inputs (ck, /ck) operation ? differential data strobe (dqs, /dqs) ? on chip dll align dq, dqs and /dqs transition with ck transition ? dm masks write data-in at the both rising and falling edges of the data strobe ? all addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock ? programmable cas latency 5, 6, 7, 8, 9, 10, and (11) supported ? programmable additive latency 0, cl-1 and cl-2 sup- ported ? programmable cas write latency (cwl) = 5, 6, 7, 8 ? programmable burst length 4/8 with both nibble sequential and interleave mode ? bl switch on the fly ? 8 banks ? 8k refresh cycles /64ms ? ddr3 sdram package: jedec standard 82ball fbga(x4/x8) with support balls ? driver strength selected by emrs ? dynamic on die termination supported ? asynchronous reset pin supported ? zq calibration supported ? tdqs (termination data strobe) supported (x8 only) ? write levelization supported ? auto self refresh supported ? 8 bit pre-fetch 1. description this hynix unbuffered small outline dual in-line memory mo dule (sodimm) series consis ts of 2gb a version ddr3 sdrams in fine ball grid array (fbga) packages on a 204 pin glass-epoxy substrate. this ddr3 unbuffered sodimm series based on 2gb a version provide a high performance 8 byte interface in 67.60mm width form factor of industry standard. it is suitable for easy interchange and addition. 1.1 device features & ordering information 1.1.1 features 1.1.2 ordering information * please contact local sales administrator for more details of part number part name density organization # of drams # of ranks materials HMT351S6AFR8C-G7/h9* 4gb 512mx64 16 2 halogen free
rev. 0.02 / apr. 2009 5 hmt351s6afr8c 1.2 speed grade & key parameters 1.3 address table mt/s ddr3-1066 ddr3-1333 unit grade -g7 -h9 tck (min) 1.875 1.5 ns cas latency 79tck trcd (min) 13.125 13.5 ns trp (min) 13.125 13.5 ns tras (min) 37.5 36 ns trc (min) 50.625 49.5 ns cl-trcd-trp 7-7-7 9-9-9 tck 4gb organization 512m x 64 refresh method 8k/64ms row address a0-a14 column address a0-a9 bank address ba0-ba2 page size 1kb # of rank 2 # of device 16
rev. 0.02 / apr. 2009 6 hmt351s6afr8c 2. pin architecture 2.1 pin definition pin name description pin name description ck[1:0] clock inputs, positive line 2 dq[63:0] data input/output 64 ck [1:0] clock inputs, negative line 2 dm[7:0] data masks 8 cke[1:0] clock enables 2 dqs[7:0] data strobes 8 ras row address strobe 1 dqs [7:0] data strobes complement 8 cas column address strobe 1 reset reset pin 1 we write enable 1 test logic analyzer specific test pin (no connect on sodimm) 1 s [1:0] chip selects 2 event temperature event pin 1 a[9:0], a11, a[14:13] address inputs 14 v dd core and i/o power 18 a10/ap address input/autoprecharge 1 v ss ground 52 a12/bc address input/burst stop 1 v ref dq input/output reference 2 ba[2:0] sdram bank address 3 v ref ca odt [1:0] on-die termination control 2 v dd spd spd and temp sensor power 1 scl serial presence detect (spd) clock input 1 vtt termination voltage 2 sda spd data input/output 1 n c reserved for future use 2 sa [1:0] spd address 2 total 204
rev. 0.02 / apr. 2009 7 hmt351s6afr8c 2.2 input/output functional description symbol type polarity function ck0/ck 0 ck1/ck 1 input cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and falling edge of ck . a delay locked loop (dll) cir- cuit is driven from the clock inputs and ou tput timing for read operations is synchro- nized to the input clock. cke[1:0] input active high activates the ddr3 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates the power down mode or the self refresh mode. s [1:0] input active low enables the associated ddr3 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new com- mands are ignored but previous operations continue. rank 0 is selected by s 0; rank 1 is selected by s 1. ras , cas , we input active low when sampled at the cross point of the rising edge of ck and falling edge of ck , sig- nals cas , ras , and we define the operation to be executed by the sdram. ba[2:0] input - selects which ddr3 sdram internal bank of eight is activated. odt[1:0] input active high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr3 sdram mode register. a[9:0], a10/ap , a11, a12/bc , a[15:13] input - during a bank activate command cycle, defines the row address when sampled at the cross point of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operat ion at the end of the burst read or write cycle. if ap is high, autoprecharge is se lected and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba0-ban to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0- ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. a12(bc ) is sampled during read and write commands to determine if burst chop (on-thefly) will be performed (high, no burst chop; low, burst chopped) dq[63:0] in/out - data input/output pins. dm[7:0] input active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect. dqs[7:0], dqs [7:0] in/out cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode, the data strobe is sourced by the ddr3 sdrams and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs .
rev. 0.02 / apr. 2009 8 hmt351s6afr8c v dd, v dd spd, v ss, supply power supplies for core, i/o, serial presence detect, temp sensor, and ground for the module. v ref dq, v ref ca supply reference voltage for sstl15 inputs. sda in/out this is a bidirectional pin used to transfer data into or out of the spd eeprom and temp sensor. a resistor must be connected from the sda bus line to v dd spd on the system planar to act as a pull up. scl input this signal is used to clock data into and out of the spd eeprom and temp sensor. sa[1:0] input address pins used to select the serial presence detect and temp sensor base address. test in/out the test pin is reserved for bus analysis tools and is not connected on normal memory modules (so-dimms). event wire or out active low the event pin is reserved for use to flag critical module temperature. a resistor may be connected from event bus line to vd dspd on the system planar to act as a pullup. reset in active low this signal resets the ddr3 sdram symbol type polarity function
rev. 0.02 / apr. 2009 9 hmt351s6afr8c 2.3 pin assignment pin # front side pin # back side pin # front side pin # back side pin # front side pin # back side pin # front sid pin # back side 1 v ref dq 2 v ss 53 dq19 54 v ss 105 v dd 106 v dd 157 dq42 158 dq46 3 v ss 4 dq4 55 v ss 56 dq28 107 a10/ap 108 ba1 159 dq43 160 dq47 5 dq0 6 dq5 57 dq24 58 dq29 109 ba0 110 ras 161 v ss 162 v ss 7dq18 v ss 59 dq25 60 v ss 111 v dd 112 v dd 163 dq48 164 dq52 9 v ss 10 dqs 0 61 v ss 62 dqs 3 113 we 114 s 0 165 dq49 166 dq53 11 dm0 12 dqs0 63 dm3 64 dqs3 115 cas 116 odt0 167 v ss 168 v ss 13 v ss 14 v ss 65 v ss 66 v ss 117 v dd 118 v dd 169 dqs 6 170 dm6 15 dq2 16 dq6 67 dq26 68 dq30 119 a13 2 120 odt1 171 dqs6 172 v ss 17 dq3 18 dq7 69 dq27 70 dq31 121 s 1 122 nc 173 v ss 174 dq54 19 v ss 20 v ss 71 v ss 72 v ss 123 v dd 124 v dd 175 dq50 176 dq55 21 dq8 22 dq12 73 cke0 74 cke1 125 test 126 v ref ca 177 dq51 178 v ss 23 dq9 24 dq13 75 v dd 76 v dd 127 v ss 128 v ss 179 v ss 180 dq60 25 v ss 26 v ss 77 nc 78 a15 2 129 dq32 130 dq36 181 dq56 182 dq61 27 dqs 1 28 dm1 79 ba2 80 a14 2 131 dq33 132 dq37 183 dq57 184 v ss 29 dqs1 30 reset 81 v dd 82 v dd 133 v ss 134 v ss 185 v ss 186 dqs 7 31 v ss 32 v ss 83 a12/bc 84 a11 135 dqs 4 136 dm4 187 dm7 188 dqs7 33 dq10 34 dq14 85 a9 86 a7 137 dqs4 138 v ss 189 v ss 190 v ss 35 dq11 36 dq15 87 v dd 88 v dd 139 v ss 140 dq38 191 dq58 192 dq62 37 v ss 38 v ss 89 a8 90 a6 141 dq34 142 dq39 193 dq59 194 dq63 39 dq16 40 dq20 91 a5 92 a4 143 dq35 144 v ss 195 v ss 196 v ss 41 dq17 42 dq21 93 v dd 94 v dd 145 v ss 146 dq44 197 sa0 198 event 43 v ss 44 v ss 95 a3 96 a2 147 dq40 148 dq45 199 vdd spd 200 sda 45 dqs 2 46 dm2 97 a1 98 a0 149 dq41 150 v ss 201 sa1 202 scl 47 dqs2 48 v ss 99 v dd 100 v dd 151 v ss 152 dqs 5 203 v tt 204 v tt 49 v ss 50 dq22 101 ck0 102 ck1 153 dm5 154 dqs5 51 dq18 52 dq23 103 ck0 104 ck1 155 v ss 156 v ss nc = no connect; rfu = reserved future use 1. test (pin 125) is reserved for bus analysis probes and is nc on normal memory modules. 2. this address might be connected to nc balls of the dram s (depending on density); ei ther way they will be con- nected to the termination resistor.
rev. 0.02 / apr. 2009 10 hmt351s6afr8c 3. 4gb, 512mx64 mo dule(2rank of x8) dqs3 dqs3 dm3 dq[24:31] dqs dqs dm dq [0:7] d11 ras cas s1 we ck1 ck1 cke1 odt1 a[o:n]/ba[o:n] 240ohm zq +/-1% vtt ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d3 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ck0 ck0 cke0 odt0 s0 a2 temp se ns or sda d0?d15 v dd spd spd/ts d0?d15 v ref ca scl v tt d0?d15 v dd event a1 a0 scl sa0 sa1 (with spd) event a2 sda scl wp a1 a0 scl sa0 sa1 (spd) v tt v ref dq v ss ck0 ck0 ck1 ck1 cke0 cke1 d0?d15, spd, temp sensor d0?d7 d8?d15 d0-d7 d8-d15 notes 1. dq wiring may differ from that shown however, dq, dm, dqs, and dqs relationships are ma intained as shown rank 0 d0?d7 d8?d15 rank 1 dqs1 dqs1 dm1 dq[8:15] dqs dqs dm dq [0:7] d1 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d9 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs0 dqs0 dm0 dq[0:7] dqs dqs dm dq [0:7] d0 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d8 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs4 dqs4 dm4 dq[32:39] dqs6 dqs6 dm6 dq[48:55] dqs7 dqs7 dm7 dq[56:43] dqs5 dqs5 dm5 dq[40:47] vtt vtt vdd vdd cterm cterm d12 d4 dqs dqs dm dq [0:7] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d6 d14 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm d7 d15 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm dqs2 dqs2 dm2 dq[6:23] dqs dqs dm dq [0:7] d2 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] ldqs ldqs ldm dq [0:7] d10 240ohm zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] d5 d13 dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] dqs dqs dm dq [0:7] zq +/-1% ras cas cs we ck ck cke odt a[o:n]/ba[o:n] 240ohm 240ohm s0 odt0 s1 odt1 event reset d0?d7 d8?d15 temp sensor d0-d15 d0?d7 d8?d15 the spd may be integrated with the temp sensor or may be a separate component d0 v1 v9 d1 d11 d2 d13 d4 d14 d15 d9 d8 d10 d3 d12 d5 d7 d6 vtt v1 v2 v3 v4 v5 v6 v8 v7 v6 v8 v7 v5 v9 v1 v4 v3 v2
rev. 0.02 / apr. 2009 11 hmt351s6afr8c 4. absolute maximum ratings 4.1 absolute maxi mum dc ratings 4.2 dram component ope rating temperature range symbol parameter rating units notes vdd voltage on vdd pin relative to vss - 0.4 v ~ 1.975 v v ,3 vddq voltage on vddq pin relative to vss - 0.4 v ~ 1.975 v v ,3 vin, vout voltage on any pin relative to vss - 0.4 v ~ 1.975 v v tstg storage temperature -55 to +100 ? ? , 2 1. stresses greater than those listed under ?absolut e maximum ratings? may cause permanent damage to the device. this is a stress rating only and function al operation of the device at these or any other conditions above those indicated in the oper ational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. storage temperature is the case surface temperature on the center/top side of the dram. for the measurement conditions, please refer to jesd51-2 standard. 3. vdd and vddq must be within 300mv of each othe r at all times; and vref must be not greater than 0.6xvddq,when vdd and vddq are less than 500mv; vref may be equal to or less than 300mv. symbol parameter rating units notes toper normal temperature range 0 to 85 ? ,2 extended temperature range 85 to 95 ? 1,3 1. operating temperature toper is the case surface temperature on the center / top side of the dram. for measurement conditions, please refer to the jedec document jesd51-2. 2. the normal temperature range specifies the temperat ures where all dram specifications will be supported. during operation, the dram case temperature must be maintained between 0 - 85oc under all operating conditions 3. some applications require operation of the dram in the extended temperature range between 85? and 95? case temperature. full specifications are guaranteed in this range, but the following additional conditions apply: a) refresh commands must be doubled in frequency, therefore reducing the refresh interval trefi to 3.9 s. (this double refresh requirement may not apply for some devices.) it is also possible to specify a component with 1x refresh (trefi to 7.8s) in the extend ed temperature range. please refer to supplier data sheet and/ or the dimm spd for option avail ability. b) if self-refresh operation is required in the extend ed temperature range, than it is mandatory to either use the manual self-refresh mode with extended temperature range capability (mr2 a6 = 0band mr2 a7 = 1b) or enable the optional auto self-refresh mode (mr2 a6 = 1b and mr2 a7 = 0b).
rev. 0.02 / apr. 2009 12 hmt351s6afr8c 5. ac & dc operating conditions 5.1 recommended dc operating conditions 5.2 dc & ac logic input levels 5.2.1 dc & ac logic input levels for single-ended signals the dc-tolerance limits and ac-noise limits for the referenc e voltages vrefca and vrefdq are illustrated in figure 5.2.1. it shows a valid reference voltage vref (t) as a fu nction of time. (vref stands for vrefca and vrefdq like- wise).vref(dc) is the linear average of vref (t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in table 1. fu rthermore vref (t) may temporarily deviate from vref (dc) by no more than +/- 1% vdd. symbol parameter rating units notes min. typ. max. vdd supply voltage 1.425 1.500 1.575 v 1,2 vddq supply voltage for output 1.425 1.500 1.575 v 1,2 1. under all conditions, vddq must be less than or equal to vdd. 2. vddq tracks with vdd. ac parameters are measured with vdd add vddq tied together. symbol parameter ddr3-1066, ddr3-1333 unit notes min max vih(dc) dc input logic high vref + 0.100 - v 1, 2 vil(dc) dc input logic low vref - 0.100 v 1, 2 vih(ac) ac input logic high vref + 0.175 - v 1, 2 vil(ac) ac input logic low vref - 0.175 v 1, 2 vrefdq (dc) reference voltage for dq, dm inputs 0.49 * vdd 0.51 * vdd v 3, 4 vrefca (dc) reference voltage for add, cmd inputs 0.49 * vdd 0.51 * vdd v 3, 4 vtt termination voltage for dq, dqs outputs vddq/2 - tbd vddq/2 + tbd v 1. for dq and dm, vref = vrefdq. for input only pins except reset#, vref = vrefca. 2. the ?t.b.d.? entries might change based on overshoot and undershoot specification. 3. the ac peak noise on vref may not allow vref to deviate from vref (dc) by more than +/-1% vdd (for reference: approx. +/- 15 mv). for reference: approx. vdd/2 +/- 15 mv.
rev. 0.02 / apr. 2009 13 hmt351s6afr8c < figure 5.2.1: illustration of vref (dc) tolerance and vref ac-noise limits > the voltage levels for setup and hold time measurements vih(ac), vih(dc), vil(ac) and vil(dc) are dependent on vref. "vref " shall be understood as vref (dc), as defined in figure. this clarifies, that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is me asured. system timing and voltage budgets need to account for vref (dc) deviations from the optimum posi tion within the data-eye of the input signals. this also clarifies that the dram setup/ hold specification and derating values ne ed to include time and voltage associ- ated with vref ac-noise. timing and volt age effects due to ac-noise on vref up to the specified limit (+/-1% of vdd) are included in dram timings and their associated deratings. 5.2.2 dc & ac logic input leve ls for differential signals note1: refer to ?overshoot and undershoot specification section 6.5 on 26 page symbol parameter ddr3-1066, ddr3-1333 unit notes min max vihdiff differential input logic high + 0.200 - v 1 vildiff differential input logic low - 0.200 v 1 vdd vss vdd/2 v ref(dc) v ref ac-noise voltage time v ref(dc)max v ref(dc)min v ref (t)
rev. 0.02 / apr. 2009 14 hmt351s6afr8c 5.2.3 differential input cross point voltage to guarantee tight setup and hold times as well as output skew parameters wi th respect to clock and strobe, each cross point voltage of differential inpu t signals (ck, ck# and dqs, dqs#) must meet the requirements in table the differential input cross point voltage vix is measured from the actual cross point of true and complement signal to the midlevel between of vdd and vss. < figure 5.2.3: vix definition > < table 5.2.3: cross point voltage for di fferential input signals (ck, dqs) > symbol parameter ddr3-1066, ddr3-1333 unit notes min max v ix differential input cross point voltage relative to vdd/2 - 150 + 150 mv vdd vss vdd/2 v ix v ix v ix ck#, dqs# ck, dqs
rev. 0.02 / apr. 2009 15 hmt351s6afr8c 5.3 slew rate definitions 5.3.1 for single ended input signals - input slew rate for input setup time (tis) and data setup time (tds) setup (tis and tds) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vref and the first crossing of vih (ac) min. setup (tis and td s) nominal slew rate for a fall ing signal is defined as the slew rate between the last crossing of vref and the first crossing of vil (ac) max. - input slew rate for input hold ti me (tih) and data hold time (tdh) hold nominal slew rate for a rising signal is defined as the slew rate between the last crossing of vi l(dc) max and the first crossing of vref. hold (tih and tdh) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of vih (d c) min and the first crossing of vref. < table 5.3.1: single-ended input slew rate definition > description measured defined by applicable for min max input slew rate for rising edge vref vih (ac) min vih (ac) min-vref delta trs setup (tis, tds) input slew rate for falling edge vref vil (ac) max vref-vil (ac) max delta tfs input slew rate for rising edge vi l(dc) max vref vref-vil (dc) max delta tfh hold (tih, tdh) input slew rate for falling edge vih (dc) min vref vih (dc) min-vref delta trh delta tfs delta trs vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca part a: set up single ended input voltage(dq,add, cmd)
rev. 0.02 / apr. 2009 16 hmt351s6afr8c < figure 5.3.1: input nominal slew rate definition for single-ended signals > 5.3.2 differential input signals input slew rate for differential signals (ck, ck# and dqs, dqs#) are defined and measured as shown in below table and figure . note: the differential signal (i.e. ck-ck and dqs-dq s) must be linear between these thresholds. description measured defined by min max differential input slew rate for rising edge (ck-ck and dqs-dqs) vildiffmax vihdiffmin vihdiffmin-vildiffmax deltatrdiff differential input slew rate for falling edge (ck-ck and dqs-dqs) vihdiffmin vildiffmax vihdiffmin-vildiffmax deltatfdiff part b: hold delta tfh delta trh vih(ac)min vih(dc)min vil(dc)max vil(ac)max vrefdq or vrefca single ended input voltage(dq,add, cmd)
rev. 0.02 / apr. 2009 17 hmt351s6afr8c < figure 5.3.2: differential input slew ra te definition for dqs,dqs# and ck,ck# > 5.4 dc & ac output buffer levels 5.4.1 single ended dc & ac output levels below table shows the output levels used for measurements of single ended signals. symbol parameter ddr3-1066, 1333 unit notes voh(dc) dc output high measurement level (for iv curve linearity) 0.8 x vddq v vom(dc) dc output mid measurement level (for iv curve linearity) 0.5 x vddq v vol(dc) dc output low measurement level (for iv curve linearity) 0.2 x vddq v voh(ac) ac output high measurement level (for output sr) vtt + 0.1 x vddq v 1 vol(ac) ac output low measurement level (for output sr) vtt - 0.1 x vddq v 1 1. the swing of ? 1 x vddq is based on approximately 50% of the static single ended output high or low swing with a driver impedance of 40 ? and an effective test load of 25 ? to vtt = vddq / 2. delta tfdiff delta trdiff vihdiffm in vildiffm ax 0 differential input voltage (i.e. dqs-dqs; ck-ck)
rev. 0.02 / apr. 2009 18 hmt351s6afr8c 5.4.2 differential dc & ac output levels below table shows the output levels used for measurements of differential signals. 5.4.3 single ended output slew rate with the reference load for timing measurements, output slew rate for falling and rising edges is defined and measured between vol(ac) and voh(ac) for single ende d signals as shown in belo w table and figure 5.4.3. note: output slew rate is verified by design and characte risation, and may not be subject to production test. < figure 5.4.3: single ended output slew rate definition > symbol parameter ddr3-1066, 1333 unit notes vohdiff (ac) ac differential output high measurement level (for output sr) + 0.2 x vddq v 1 voldiff (ac) ac differential output low measurement level (for output sr) - 0.2 x vddq v 1 1. the swing of ? 0.2 x vddq is based on appro ximately 50% of the static differential output high or low swing with a driver impedance of 40?? and an effective test load of 25?? to vtt = vddq/2 at each of the differential output description measured defined by from to single ended output slew rate for rising edge vol(ac) voh(ac) voh(ac)-vol(ac) deltatrse single ended output slew rate for falling edge voh(ac) vol(ac) voh(ac)-vol(ac) deltatfse delta tfse delta trse voh(ac) vol(ac) v ? single ended output voltage(l.e.dq)
rev. 0.02 / apr. 2009 19 hmt351s6afr8c *** description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) for ron = rzq/7 setting < table 5.4.3: output slew rate (single-ended) > 5.4.4 differential output slew rate with the reference load for timing measurements, output sl ew rate for falling and rising edges is defined and mea- sured between voldiff (ac) and vohdiff (ac) for differen tial signals as shown in below table and figure 5.4.4 note: output slew rate is verified by design and charac terization, and may not be subject to production test.. < figure 5.4.4: differential output slew rate definition > parameter symbol ddr3-1066 ddr3-1333 units min max min max single-ended output slew rate srqse 2.5 5 2.5 5 v/ns description measured defined by from to differential output slew rate for rising edge voldiff (ac) vohdiff (ac) vohdiff (ac)-voldiff (ac) deltatrdiff differential output slew rate for falling edge vohdiff (ac) voldiff (ac) vohdiff (ac)-voldiff (ac) deltatfdiff delta tfdiff delta trdiff voldiff(ac) o differential output voltage(i.e. dqs-dqs) vohdiff(ac)
rev. 0.02 / apr. 2009 20 hmt351s6afr8c ***description: sr: slew rate q: query output (like in dq, which stands for data-in, query-output) diff: differential signals for ron = rzq/7 setting < table 5.4.4: differential output slew rate > 5.5 overshoot and undershoot specifications 5.5.1 address and control overshoot and undershoot specifications < table 5.5.1: ac overshoot/undershoot sp ecification for address and control pins > < figure 5.5.1: address and control overshoot and undershoot definition > parameter symbol ddr3-1066 ddr3-1333 units min max min max differential output slew rate srqdiff 5 10 5 10 v/ns description specification ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v maximum overshoot area above vdd (see figure) 0.5 v-ns 0.4 v-ns maximum undershoot area below vss (see figure) 0.5 v-ns 0.4 v-ns maximum amplitude overshoot area vdd vss volts (v) maximum amplitude undershoot area time (ns)
rev. 0.02 / apr. 2009 21 hmt351s6afr8c 5.5.2 clock, data, strobe and mask overshoot and undershoot specifications < table 5.5.2: ac overshoot/undershoot specification for clock, data, strobe and mask > < figure 5.5.2: clock, data, strobe and mask overshoot and undershoot definition > description specification ddr3-1066 ddr3-1333 maximum peak amplitude allowed for overshoot area (see figure) 0.4v 0.4v maximum peak amplitude allowed for undershoot area (see figure) 0.4v 0.4v maximum overshoot area above vddq (see figure) 0.19 v-ns 0.15 v-ns maximum undershoot area below vssq (see figure) 0.19 v-ns 0.15 v-ns m axim um am plitude overshoot area vddq vssq maximum amplitude undershoot area time (ns) clock, data strobe and mask overshoot and undershoot definition volts (v)
rev. 0.02 / apr. 2009 22 hmt351s6afr8c 5.6 pin capacitance parameter symbol ddr3-1066 ddr3-1333 units notes min max min max input/output capacitance (dq, dm, dqs, dqs#, tdqs, tdqs#) c io tbd tbd tbd tbd pf 1,2,3 input capacitance, ck and ck# c ck tbd tbd tbd tbd pf 2,3,5 input capacitance delta ck and ck# c dck tbd tbd tbd tbd pf 2,3,4 input capacitance (all other input-only pins) c i tbd tbd tbd tbd pf 2,3,6 input capacitance delta, dqs and dqs# c ddqs tbd tbd tbd tbd pf 2,3,12 input capacitance delta (all ctrl input-only pins) c di_ctrl tbd tbd tbd tbd pf 2,3,7,8 input capacitance delta (all add/cmd input-only pins) c di_add_cmd tbd tbd tbd tbd pf 2,3,9, 10 input/output capacitance delta (dq, dm, dqs, dqs#) c dio tbd tbd tbd tbd pf 2,3,11 notes: 1. tdqs/tdqs# are not necessarily input function but since tdqs is sharing dm pin and the parasitic characterization of tdqs/tdqs# should be close as much as possible, cio & cdio requirement is applied (recommend deleting note or changing to ?although the dm, tdqs and tdqs# pins have different functions, the loading matches dq and dqs.?) 2. this parameter is not subject to production test. it is verified by design and characterization. input capacitance is measured according to jep147(?procedure for measuring input capacitance using a vector network analyzer(vna)?) with vdd, vddq, vss,vssq applied an d all other pins floating (except the pin under test, cke, reset# and odt as necessary). vdd=vddq=1.5v, vbias=vdd/2 and on-die termination off. 3. this parameter applies to monolithic devices only; stacked/dual-die devices are not covered here 4. absolute value of c ck -c ck #. 5. the minimum c ck will be equal to the minimum c i . 6. input only pins include: odt, cs, cke, a0-a15, ba0-ba2, ras#, cas#, we#. 7. ctrl pins defined as odt, cs and cke. 8. c di_ctrl =c i (cntl) - 0.5 * c i (clk) + c i (clk#)) 9. add pins defined as a0-a15, ba0-ba2 and cmd pins are defined as ras#, cas# and we#. 10. c di_add_cmd =c i (add_cmd) - 0.5*(c i (clk)+c i (clk#)) 11. c dio =c io (dq) - 0.5*(c io (dqs)+c io (dqs#)) 12. absolute value of c io (dqs) - c io (dqs#)
rev. 0.02 / apr. 2009 23 hmt351s6afr8c 5.7 idd specifications (t case : 0 to 95 o c) 4gb, 512m x 64 so-dimm: hmt351s6afrp8 c symbol ddr3 1066 ddr3 1333 unit note i dd0 960 1040 ma x8 i dd1 1040 1120 ma x8 i dd2n 720 800 ma x8 i dd2nt 800 880 ma x8 i dd2p0 192 192 ma x8 i dd2p1 480 560 ma x8 i dd2q 720 800 ma x8 i dd3n 880 960 ma x8 i dd3p 560 560 ma x8 i dd4r 1480 1640 ma x8 i dd4w 1520 1680 ma x8 i dd5b 2040 2080 ma x8 i dd6 192 192 ma x8 i dd6et 240 240 ma x8 i dd6tc 240 240 ma x8 i dd7 2040 2240 ma x8
rev. 0.02 / apr. 2009 24 hmt351s6afr8c 5.7 idd measurement conditions in this chapter, idd and iddq measurement conditions such as test load and patterns are defined. figure 1. shows the setup and test load for idd and iddq measurements. ? idd currents (such as idd0, idd1, idd2n, idd2nt, i dd2p0, idd2p1, idd2q, idd3n, idd3p, idd4r, idd4w, idd5b, idd6, idd6et, idd6tc and i dd7) are measured as time-averaged cu rrents with all vdd balls of the ddr3 sdram under test tied together. any iddq current is not included in idd currents. ? iddq currents (such as iddq2nt and iddq4r) are measur ed as time-averaged currents with all vddq balls of the ddr3 sdram under test tied together. any i dd current is not included in iddq currents. attention: iddq values cannot be di rectly used to calculate io power of the ddr3 sdram. they can be used to support correlation of simulated io power to actual io po wer as outlined in figure 2. in dram module application, iddq cannot be measured separately since vdd and vddq are using one merged-power layer in module pcb. for idd and iddq measurements, the following definitions apply: ? ?0? and ?low? is defined as vin <= v ilac(max). ? ?1? and ?high? is defined as vin >= v ihac(max). ? ?floating? is defined as inputs are vref - vdd/2. ? timing used for idd and iddq me asurement-loop patterns are provided in table 1 on page 26. ? basic idd and iddq measurement conditi ons are described in table 2 on page 26. ? detailed idd and iddq meas urement-loop patterns are described in table 3 on page 30 through table 10 on page 36. ? idd measurements are done after properly initializing the ddr3 sdram. this includes but is not limited to setting ron = rzq/7 (34 ohm in mr1); qoff = 0 b (output buffer enabled in mr1); rtt_nom = rzq/6 (40 ohm in mr1); rtt_wr = rzq/2 (120 ohm in mr2); tdqs feature disabled in mr1 ? attention: the idd and iddq measurement-loop patterns need to be executed at least one time before actual idd or iddq measur ement is started. ? define d = {cs , ras , cas , we }:= {high, low, low, low} ? define d = {cs , ras , cas , we }:= {high, high, high, high}
rev. 0.02 / apr. 2009 25 hmt351s6afr8c figure 1 - measurement setup and test load for idd and iddq (optional) measurements [note: dimm level output test load condition may be different from above] figure 2 - correlation from simulated channel io power to actual channel io power supported by iddq measurement v dd ddr3 sdram v ddq reset ck/ck dqs, dqs cs ras , cas , we a, ba odt zq v ss v ssq dq, dm, tdqs, tdqs cke r tt = 25 ohm v ddq /2 i dd i ddq (optional) application specific memory channel environment channel io power simulation iddq simulation iddq simulation channel io power number iddq test load correction
rev. 0.02 / apr. 2009 26 hmt351s6afr8c table 1 -timings used for idd and iddq measurement-loop patterns table 2 -basic idd and iddq measurement conditions symbol ddr3-1066 ddr3-1333 unit 7-7-7 9-9-9 t ck 1.875 1.5 ns cl 7 9 nck n rcd 79nck n rc 27 33 nck n ras 20 24 nck n rp 79nck n faw x4/x8 20 20 nck x16 27 30 nck n rrd x4/x8 4 4 nck x16 6 5 nck n rfc -512mb 48 60 nck n rfc -1 gb 59 74 nck n rfc - 2 gb 86 107 nck n rfc - 4 gb 160 200 nck n rfc - 8 gb 187 234 nck symbol description i dd0 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between act and pre; command, address, bank addre ss inputs: partially toggling according to table 3 on page 30; data io: floating; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see table 3 on page 30); outp ut buffer and rtt: enabl ed in mode registers b) ; odt signal: stable at 0; pattern details: see table 3 on page 30 i dd1 operating one bank active-precharge current cke: high; external clock: on; tck, nrc, nras, nrcd, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between act, rd and pre; command, address; bank address inputs, data io: partially toggling according to table 4 on page 31; dm: stable at 0; ba nk activity: cycling with on bank active at a time: 0,0,1,1,2,2,... (see table 4 on pa ge 31); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 4 page 31
rev. 0.02 / apr. 2009 27 hmt351s6afr8c i dd2n precharge standby current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling a ccording to table 5 on page 32; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 32 i dd2nt precharge standby odt current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling a ccording to table 6 on page 32; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: toggling according to table 6 on page 32; pattern details: see table 6 on page 32 i ddq2nt (optional ) precharge standby odt iddq current same definition like for idd2nt, however meas uring iddq current instead of idd current i dd2p0 precharge power-down current slow exit cke: low; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: slow exit c) i dd2p1 precharge power-down current fast exit cke: low; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io : floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; precharge power down mode: fast exit c) i dd2q precharge quiet standby current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i ddq4r (optional ) operating burst read iddq current same definition like for idd4r, however meas uring iddq current instead of idd current
rev. 0.02 / apr. 2009 28 hmt351s6afr8c i dd3n active standby current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: partially toggling a ccording to table 5 on page 32; data io: floating; dm: stable at 0; bank activity: all banks open; ou tput buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 5 on page 32 i dd3p active power-down current cke: low; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : stable at 1; command, address, bank address inputs: stable at 0; data io: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0 i dd4r operating burst read current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between rd; command, address, bank address i nputs: partially toggling according to table 7 on page 33; data io: seamless read data burst with different data betw een one burst and the next one according to table 7 on page 33; dm: stable at 0; bank activity: al l banks open, rd commands cycling through banks: 0,0,1,1,2,2,...(see tabl e 7 on page 33); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 7 on page 33 i dd4w operating burst write current cke: high; external clock: on; tck, cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between wr; command, address, bank address i nputs: partially toggling according to table 8 on page 34; data io: seamless read data burst with different data betw een one burst and the next one according to table 8 on page 34; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,...(see tabl e 8 on page 34); output buffer and rtt: enabled in mode registers b) ; odt signal: stable at high; pattern details: see table 8 on page 34 i dd5b burst refresh current cke: high; external clock: on; tck, cl, nrfc: see table 1 on page 26; bl: 8 a) ; al: 0; cs : high between ref; command, address, bank addr ess inputs: partially toggling according to table 9 on page 35; data io: floating; dm: stable at 0; bank activity: ref command every nref (see table 9 on page 35); out- put buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 9 on page 35
rev. 0.02 / apr. 2009 29 hmt351s6afr8c a) burst length: bl8 fixed by mrs: set mr0 a[1,0]=00b b) output buffer enable: set mr1 a[12] = 0b; set mr1 a[ 5,1] = 01b; rtt_nom enable: set mr1 a[9,6,2] = 011b; rtt_wr enable: set mr2 a[10,9] = 10b c) precharge power down mode: set mr0 a12=0b for slow exit or mr0 a12 = 1b for fast exit d) auto self-refresh (asr): set mr2 a6 = 0b to disable or 1b to enable feature e) self-refresh temperature range (srt): set mr2 a7 = 0b for normal or 1b for extended temperature range f) refer to dram supplier data sheet and/ or dimm spd to determine if optional features or requirements are supported by ddr3 sdram device i dd6 self-refresh current: normal temperature range t case : 0 - 85 o c; auto self-refre sh (asr): disabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs , com- mand, address, bank address inputs, data io: floati ng; dm: stable at 0; bank activity: self-refresh operation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6et self-refresh current: extended temperature range (optional) f) t case : 0 - 95 o c; auto self-refresh (asr): disabled d) ;self-refresh temperature range (srt): extend- ed e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs , command, address, bank address i nputs, data io: floating; dm: stabl e at 0; bank activity: extended temperature self-refresh oper ation; output buffer and rtt: enabled in mode registers b) ; odt signal: floating i dd6tc auto self-refresh current (optional) f) t case : 0 - 95 o c; auto self-refre sh (asr): enabled d) ;self-refresh temperature range (srt): normal e) ; cke: low; external clock: off; ck and ck : low; cl: see table 1 on page 26; bl: 8 a) ; al: 0; cs , com- mand, address, bank address inputs, data io: floa ting; dm: stable at 0; bank activity: auto self- refresh operation; output buffer a nd rtt: enabled in mode registers b) ; odt signal: floating i dd7 operating bank interleave read current cke: high; external clock: on; tck, nrc, nras, nrcd, nrrd, nfaw, cl: see table 1 on page 26; bl: 8 a) ; al: cl-1; cs : high between act and rda; command, addre ss, bank address inputs: partially tog- gling according to table 10 on page 36; data io: re ad data burst with different da ta between one burst and the next one according to table 10 on page 36; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1,...7) with different addressing, wee table 10 on page 36; output buffer and rtt: enabled in mode registers b) ; odt signal: stable at 0; pattern details: see table 10 on page 36
rev. 0.02 / apr. 2009 30 hmt351s6afr8c table 3 - idd0 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 0 0 - ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 00 00 0 0 f 0 - ... repeat pattern 1...4 until 1*nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern 1...4 until 2*nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.02 / apr. 2009 31 hmt351s6afr8c table 4 - idd1 measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1,2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 00000 0 0 - ... repeat pattern 1...4 until nrcd - 1, truncate if necessary nrcd rd 0 1 0 1 0 0 00 0 0 0 0 0000000 0 ... repeat pattern 1...4 until nras - 1, truncate if necessary nras pre 0 0 1 0 0 0 00 0 0 0 0 - ... repeat pattern 1...4 until nrc - 1, truncate if necessary 1*nrc+0 act 0 0 1 1 0 0 00 0 0 f 0 - 1*nrc+1,2 d, d 1 0 0 0 0 0 00 0 0 f 0 - 1*nrc+3,4 d , d 1111 0 00000 f 0 - ... repeat pattern nrc + 1,...4 until n rc + nrce - 1, truncate if necessary 1*nrc+nrcd rd 0 1 0 1 0 0 00 0 0 f 0 0011001 1 ... repeat pattern nrc + 1,...4 until nrc + nras - 1, truncate if necessary 1*nrc+nras pre 0 0 1 0 0 0 00 0 0 f 0 - ... repeat pattern nrc + 1,...4 until *2 nrc - 1, truncate if necessary 1 2*nrc repeat sub-loop 0, use ba[2:0] = 1 instead 2 4*nrc repeat sub-loop 0, use ba[2:0] = 2 instead 3 6*nrc repeat sub-loop 0, use ba[2:0] = 3 instead 4 8*nrc repeat sub-loop 0, use ba[2:0] = 4 instead 5 10*nrc repeat sub-loop 0, use ba[2:0] = 5 instead 6 12*nrc repeat sub-loop 0, use ba[2:0] = 6 instead 7 14*nrc repeat sub-loop 0, use ba[2:0] = 7 instead
rev. 0.02 / apr. 2009 32 hmt351s6afr8c table 5 - idd2n and idd3n measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. table 6 - idd2nt and iddq2n t measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d 10000000000 - 1 d 1000000 0 0 00 - 2d 111100000f0 - 3d 111100000f0 - 1 4-7 repeat sub-loop 0, use ba[2:0] = 1 instead 2 8-11 repeat sub-loop 0, use ba[2:0] = 2 instead 3 12-15 repeat sub-loop 0, use ba[2:0] = 3 instead 4 16-19 repeat sub-loop 0, use ba[2:0] = 4 instead 5 20-23 repeat sub-loop 0, use ba[2:0] = 5 instead 6 24-17 repeat sub-loop 0, use ba[2:0] = 6 instead 7 28-31 repeat sub-loop 0, use ba[2:0] = 7 instead ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 d10000000000 - 1d10000000000- 2d 1111 0 0 0 0 0 f 0 - 3d 1111 0 0 0 0 0 f 0 0000000 0 1 4-7 repeat sub-loop 0, but odt = 0 and ba[2:0] = 1 2 8-11 repeat sub-loop 0, but odt = 1 and ba[2:0] = 2 3 12-15 repeat sub-loop 0, but odt = 1 and ba[2:0] = 3 4 16-19 repeat sub-loop 0, but odt = 0 and ba[2:0] = 4 5 20-23 repeat sub-loop 0, but odt = 0 and ba[2:0] = 5 6 24-17 repeat sub-loop 0, but odt = 1 and ba[2:0] = 6 7 28-31 repeat sub-loop 0, but odt = 1 and ba[2:0] = 7
rev. 0.02 / apr. 2009 33 hmt351s6afr8c table 7 - idd4r and iddq24 rmeasurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 rd 0 1 0 1 0 0 00 0 0 0 0 000000 00 1d100000000000- 2,3 d ,d 1111 0 0000 0 0 0 - 4rd0101000000f0 001100 11 5d1000000000f0- 6,7 d ,d 1111 0 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.02 / apr. 2009 34 hmt351s6afr8c table 8 - idd4w measurement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are used according to wr commands, otherwise floating. b) burst sequence driven on each dq signal by write command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 wr 0 1 0 0 1 0 00 0 0 0 0 000000 00 1d100010000000- 2,3 d ,d 1111 1 0000 0 0 0 - 4wr0100100000f0 001100 11 5d1000100000f0- 6,7 d ,d 1111 1 0000 0 f 0 - 1 8-15 repeat sub-loop 0, but ba[2:0] = 1 2 16-23 repeat sub-loop 0, but ba[2:0] = 2 3 24-31 repeat sub-loop 0, but ba[2:0] = 3 4 32-39 repeat sub-loop 0, but ba[2:0] = 4 5 40-47 repeat sub-loop 0, but ba[2:0] = 5 6 48-55 repeat sub-loop 0, but ba[2:0] = 6 7 56-63 repeat sub-loop 0, but ba[2:0] = 7
rev. 0.02 / apr. 2009 35 hmt351s6afr8c table 9 - idd5b measur ement-loop pattern a) a) dm must be driven low all the time. dqs, dqs are floating. b) dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 ref 0 0 0 1 0 0 0 0 0 0 0 - 11.2 d, d 1 0 0 0 0 0 00 0 0 0 0 - 3,4 d , d 1111 0 0000 0 f 0 - 5...8 repeat cycles 1. ..4, but ba[2:0] = 1 9...12 repeat cycles 1. ..4, but ba[2:0] = 2 13...16 repeat cycles 1...4, but ba[2:0] = 3 17...20 repeat cycles 1...4, but ba[2:0] = 4 21...24 repeat cycles 1...4, but ba[2:0] = 5 25...28 repeat cycles 1...4, but ba[2:0] = 6 29...32 repeat cycles 1...4, but ba[2:0] = 7 2 33...nrfc-1 repeat sub-loop 1, until nrfc - 1. truncate, if necessary.
rev. 0.02 / apr. 2009 36 hmt351s6afr8c table 10 - idd7 meas urement-loop pattern a) attention! sub-loops 10-19 have inverse a[6:3] pattern and data pattern than sub-loops 0-9 a) dm must be driven low all the time. dqs, dqs are used according to rd commands, otherwise floating. b) burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. ck, ck cke sub-loop cycle number command cs ras cas we odt ba[2:0] a[15:11] a[10] a[9:7] a[6:3] a[2:0] data b) toggling static high 0 0 act 0 0 1 1 0 0 00 0 0 0 0 - 1 rda 0 1 0 1 0 0 00 1 0 0 0 00000000 2d100000000000- ... repeat above d command until nrrd - 1 1 nrrd act 0 0 1 1 0 1 00 0 0 f 0 - nrrd+1 rda 0 1 0 1 0 1 00 1 0 f 0 00110011 nrrd+2 d 1 0 0 0 0 1 00 0 0 f 0 - ... repeat above d command until 2* nrrd - 1 2 2*nrrd repeat sub-loop 0, but ba[2:0] = 2 3 3*nrrd repeat sub-loop 1, but ba[2:0] = 3 4 4*nrrd ... d1000030000f0 - assert and repeat above d command until nfaw - 1, if necessary 5 nfaw repeat sub-loop 0, but ba[2:0] = 4 6 nfaw+nrrd repeat sub-loop 1, but ba[2:0] = 5 7 nfaw+2*nrrd repeat sub-loop 0, but ba[2:0] = 6 8 nfaw+3*nrrd repeat sub-loop 1, but ba[2:0] = 7 9 nfaw+4*nrrd ... d1000070000f0 - assert and repeat above d command until 2* nfaw - 1, if necessary 10 2*nfaw+0 act 0 0 1 1 0 0 00 0 0 f 0 - 2*nfaw+1 rda 0 1 0 1 0 0 00 1 0 f 0 00110011 2&nfaw+2 d1000000000f0 - repeat above d command until 2* nfaw + nrrd - 1 11 2*nfaw+nrrd act 0 0 1 1 0 1 00 0 0 0 0 - 2*nfaw+nrrd+1 rda 0 1 0 1 0 1 00 1 0 0 0 00000000 2&nfaw+nrrd+ 2 d100001000000 - repeat above d command until 2* nfaw + 2* nrrd - 1 12 2*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 2 13 2*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 3 14 2*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 3* nfaw - 1, if necessary 15 3*nfaw repeat sub-loop 10, but ba[2:0] = 4 16 3*nfaw+nrrd repeat sub-loop 11, but ba[2:0] = 5 17 3*nfaw+2*nrrd repeat sub-loop 10, but ba[2:0] = 6 18 3*nfaw+3*nrrd repeat sub-loop 11, but ba[2:0] = 7 14 3*nfaw+4*nrrd d100000000000 - assert and repeat above d command until 4* nfaw - 1, if necessary
rev. 0.02 / apr. 2009 37 hmt351s6afr8c 6. electrical characteristics and ac timing 6.1 refresh parameters by device density parameter symbol 512mb 1gb 2gb 4gb 8gb units ref command to act or ref command time trfc 90 110 160 300 350 ns average periodic refresh interval trefi 0 c < t case < 85 c 7.8 7.8 7.8 7.8 7.8 us 85 c < t case < 95 c 3.9 3.9 3.9 3.9 3.9 us
rev. 0.02 / apr. 2009 38 hmt351s6afr8c 6.2 ddr3 sdram standard speed bins includ e tck, trcd, trp, tr as and trc for each corresponding bin ddr3 1066 speed bin ddr3-1066f unit note cl - nrcd - nrp 7-7-7 parameter symbol min max internal read command to first data t aa 13.125 20 ns act to internal read or write delay time t rcd 13.125 ? ns pre command period t rp 13.125 ? ns act to act or ref command period t rc 50.625 ? ns act to pre command period t ras 37.5 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1)2)3)4)6) cwl = 6 t ck(avg) reserved ns 4) cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1)2)3)6) cwl = 6 t ck(avg) reserved ns 1)2)3)4) cl = 7 cwl = 5 t ck(avg) reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 ns 1)2)3)4) cl = 8 cwl = 5 t ck(avg) reserved ns 4) cwl = 6 t ck(avg) 1.875 < 2.5 ns 1)2)3) supported cl settings 6, 7, 8 n ck supported cwl settings 5, 6 n ck
rev. 0.02 / apr. 2009 39 hmt351s6afr8c ddr3 1333 speed bin ddr3-1333h unit note cl - nrcd - nrp 9-9-9 parameter symbol min max internal read command to first t aa 13.5 20 ns act to internal read or write delay time t rcd 13.5 ? ns pre command period t rp 13.5 ? ns act to act or ref command period t rc 49.5 ? ns act to pre command period t ras 36 9 * trefi ns cl = 5 cwl = 5 t ck(avg) reserved ns 1,2,3,4,7 cwl = 6, 7 t ck(avg) reserved ns 4 cl = 6 cwl = 5 t ck(avg) 2.5 3.3 ns 1,2,3,7 cwl = 6 t ck(avg) reserved ns 1,2,3,4,7 cwl = 7 t ck(avg) reserved ns 4 cl = 7 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,4,7 (optional) note 9.10 cl = 8 cwl = 5 t ck(avg) reserved ns 4 cwl = 6 t ck(avg) 1.875 < 2.5 ns 1,2,3,7 cwl = 7 t ck(avg) reserved ns 1,2,3,4 cl = 9 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3,4 cl = 10 cwl = 5, 6 t ck(avg) reserved ns 4 cwl = 7 t ck(avg) 1.5 <1.875 ns 1,2,3 (optional) ns 5 supported cl settings 6, 7, 8, 9 n ck supported cwl settings 5, 6, 7 n ck
rev. 0.02 / apr. 2009 40 hmt351s6afr8c *speed bin table notes * absolute specification (t oper ; v ddq = v dd = 1.5v +/- 0.075 v); notes: 1. the cl setting and cwl setting resu lt in tck(avg).min and tck(avg).max requirements. when making a selection of tck (avg), both need to be fulfilled: requirements from cl setting as well as requirements from cwl setting. 2. tck(avg).min limits: since cas latency is not purely an alog - data and strobe output are synchronized by the dll - all possible intermediate frequencies may not be gu aranteed. an application should use the next smaller jedec standard tck (avg) value (2.5, 1.875, 1.5, or 1.25 ns) when calculating cl [nck] = taa [ns] / tck (avg) [ns], rounding up to the next ?supported cl?. 3. tck(avg).max limits: calculate tck (avg) = taa.max / cl selected and round the result ing tck (avg) down to the next valid speed bin (i.e. 3.3ns or 2.5ns or 1.875 ns or 1.25 ns). this result is tck(avg).max corresponding to clselected. 4. ?reserved? settings are not allowed. user must program a different value. 5. ?optional? settings allow certain devices in the industry to support this setting, however, it is not a mandatory feature. refer to supplier?s data sheet and sp d information if and how this setting is supported. 6. any ddr3-1066 speed bin also support s functional operation at lower freque ncies as shown in the table which are not subject to production tests but verified by design/characterization. 7. any ddr3-1333 speed bin also supports functional operat ion at lower frequencies as shown in the table which are not subject to production tests bu t verified by design/characterization. 8. any ddr3-1600 speed bin also support s functional operation at lower freque ncies as shown in the table which are not subject to production tests bu t verified by design/characterization.
rev. 0.02 / apr. 2009 41 hmt351s6afr8c 7. dimm outline diagram 7.1 512mx64 - hmt351s6afr8c front view back view 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a spd 3.80mm max side 4.00 0.10 1.65 0.10 1.00 mm 0.08 0.20 2.55 0.60 0.45 detail of contacts a 0.10 2.55 1.00 detail of contacts b 0.3 0.3~1.0 3.00 4.00 0.15 0.05 1.80 0.10 2 x detail-b
rev. 0.02 / apr. 2009 42 hmt351s6afr8c 7.1 512mx64 - hmt 351s6afr8c (with temperature sensor) front view back view 30.0mm 67.60mm 20.0mm 6.00 2.0 21.00 39.00 2.15 3.00 pin 1 pin 203 detail- a 3.80mm max side 4.00 0.10 1.65 0.10 1.00 mm 0.08 0.20 2.55 0.60 0.45 detail of contacts a 0.10 2.55 1.00 detail of contacts b 0.3 0.3~1.0 3.00 4.00 0.15 0.05 1.80 0.10 2 x detail-b spd (ts)

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